1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications. More specifically the invention relates to the field of etching of microelectronics layers employed within microelectronics fabrications.
2. Description of the Related Art
Microelectronics devices are fabricated from layers of microelectronics materials formed sequentially upon substrates. Many of the layers are employed in patterns which must be held to fine tolerances dimensionally and compositionally. As the need for increasing component density within the microelectronics devices has grown, the dimensional requirements have also become more stringent. Likewise, the increased component density has led to the need for multiple levels of patterned conductor layers to interconnect the various circuits and components.
The conductor layers are commonly insulated from each other by inter-level metal dielectric (IMD) layers which must be formed to a high degree of surface planarity to permit high resolution patterns to be formed in upper-lying conductor layers with photolithographic methods as are well known and practiced in the art of microelectronics fabrications. To facilitate the formation of patterned conductor layers, it is often desirable to form over the conductor layer a second layer of another conductive material such as, for example, titanium nitride (TiN), which can serve as an anti-reflection coating (ARC) during photolithographic fabrication of the patterned conductor layer. Such additional surface layers are also sometimes formed on conductor layers to act as barrier layers against subsequent deleterious reactions.
It is highly desirable to minimize capacitance between conductor layers, and such inter-level metal dielectric (IMD) layers commonly are formed of multiple layers of dielectric materials wherein one or more dielectric layers are deposited possessing a particular property such as conformality followed by another material for dielectric properties such as, for instance, low dielectric constant. Often in sophisticated microelectronics devices the underlying topography is sufficiently varied at higher levels of fabrication that it is necessary to planarize further the IMD layer after formation. It is also a requirement that after formation of a planar IMD layer a series of contact via holes must be formed therein to permit interconnection of conductor layers. The formation of low resistance electrical contacts to conductor layers is sometimes facilitated by the formation of additional contact layers on the conductor layer.
Satisfactory IMD layers are formed within microelectronics fabrications employing combinations of dielectric materials such as silicon oxides formed by chemical vapor deposition (CVD) methods and silicon containing glass dielectric materials formed employing spin-on-glass (SOG) low constant dielectric materials. However, the IMD layers so formed are not without problems. For example, planarization of such IMD layers is commonly done by plasma etching methods at elevated temperatures. However, the SOG method inherently tends to form somewhat planar surfaces with resulting variations in IMD thickness over differing topographies and densities of surface features, hence it is necessary to minimize overetching of the IMD layer to avoid etching damage to an underlying ARC or barrier layer. It is also desirable to have a high selectivity of etch rate of the IMD SOG dielectric material over that of any underlying layer material to restrict the etch back reaction essentially to the IMD layer.
It is thus towards the goal of forming over substrates with topographic and pattern variations an inter-level metal dielectric (IMD) layer with improved planarization by subtractive etching back of the dielectric layer with attenuated damage to underlying material such as ARC or barrier layers that the present invention is generally directed.
Various methods have been disclosed for forming and planarizing an IMD layer employing SOG dielectric layer overlying a conductor layer by etching back the dielectric layer.
For example, Jones et al., in U.S. Pat. No. 5,549,786, disclose a method for forming a planarized surface layer of spin-on-glass (SOG) dielectric material with optimized etch selectivity with respect to underlying silicon nitride dielectric layers. The method employs a plasma sustained in a mixture of CHF3, N2 and He gases to etch back the SOG layer with a high etch rate selectivity over that of silicon nitride.
Further, Wu et al., in U.S. Pat. No. 5,747,381, discloses a method for forming a sacrificial layer of spin-on-glass (SOG) dielectric material over an inter-level dielectric (ILD) layer which is planarized by fully etching back the sacrificial SOG layer. The method employs a reactive ion etch (RIE) process to fully etch back the SOG layer into the ILD layer, both of which have comparable etch rates to the RIE environment. Any residual SOG may be further removed by wet etching in a buffered RF etch in which the SOG etches about 40 times faster than the ILD layer.
Still further, Huang et al., in U.S. Pat. No. 5,747,382, disclose a method for forming an inter-level metal dielectric (IMD) layer with attenuated void induced damage after planarization. The method employs chemical mechanical polish (CMP) planarization to open the voids and subsequent reactive ion etching after formation of the IMD layer to passivate and clean the voids.
Yet still further, Wang et al., in U.S. Pat. No. 5,792,705, disclose a method for forming a void-free dielectric layer over patterned conductor lines with a planar surface. The method employs formation of a dual dielectric liner layer of a first silicon oxide layer and then a second silicon nitride layer over the conductor lines, followed by formation of a spin-on-glass (SOG) layer over the lines. The resulting inter-level metal dielectric (IMD) layer is then etched back employing reactive ion etching to expose the underlying silicon nitride layer. After removal of the silicon nitride layer by reactive ion etching, a third dielectric layer is formed over the planarized surface.
Finally, Pu et al., in U.S. Pat. No. 5,843,847, disclose a method for etching a dielectric layer on a substrate providing high etching selectivity, high etch rates and low etch rate micro-loading. The method employs a plasma sustained in etching gases comprising fluorocarbon, carbon and nitrogen containing gases, and the use of inert gases such as helium is mentioned as an etch rate enhancement due to sputtering removal of the dielectric material by the inert gas ions.
Desirable in the art of microelectronics fabrication are additional methods for forming an IMD layer employing SOG dielectric material wherein the surface is planarized by means of plasma etch back method. More desirable are additional methods for planarizing by etching back IMD layers without damage to underlying anti-reflection and barrier layers such as titanium nitride (TiN) on conductor layers.
It is towards these goal that the present invention is generally and specifically directed.
It is a first object of the present invention to provide a method for forming on a substrate an inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material with a planarized surface and attenuated damage to underlying layers.
It is a second object of the present invention to provide a method in accord withxe2x80x94the first object of the present invention, where a plasma etch back method is employed to form the planarized surface of the SOG dielectric layer.
It is a third object of the present invention to provide a method in accord with the first object of the present invention and the second object of the present invention, where the method is readily commercially implemented.
In accord with the present invention, there is provided a method for forming upon a substrate employed within a microelectronics fabrication a planarized inter-level metal dielectric (IMD) layer employing spin-on-glass (SOG) dielectric material, with attenuated damage to underlying layers due to over-etching of the dielectric layer. There is provided a substrate upon which is formed a patterned microelectronics layer over which is formed an inter-level metal dielectric (IMD) layer comprising a first silicon oxide dielectric layer and a second dielectric layer formed employing spin-on-glass (SOG) dielectric material The IMD layer is planarized by plasma etch back process employing a plasma reactive etch cycle interrupted by an inert gas flushing step and backside cooling of the substrate employing helium coolant gas to control substrate temperature and etching reaction rates, resulting in attenuated damage to underlying layers from over-etching of the IMD layer.
The present invention may be practiced on dielectric layers formed employing SOG materials deposited upon substrates employed within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications, flat panel display microelectronics fabrications and optoelectronics display microelectronics fabrications.
The present invention may be practiced to particular advantage over substrates of varying surface topography and circuit density where the thickness of SOG layers is known to be variable. In such cases, the likelihood of removal of all of the SOG material where it is thinner is great, and a high selectivity ratio for etching SOG over an underlying barrier or ARC layer is highly desirable.
The present invention employs methods and materials which are known in the art of microelectronics fabrication, although in a novel order and sequence. There-fore the present invention is readily commercially implemented.